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Espressif Systems /ESP32 /SENS /SAR_READ_CTRL2

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Interpret as SAR_READ_CTRL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SAR2_CLK_DIV0SAR2_SAMPLE_CYCLE0SAR2_SAMPLE_BIT 0 (SAR2_CLK_GATED)SAR2_CLK_GATED 0SAR2_SAMPLE_NUM0 (SAR2_PWDET_FORCE)SAR2_PWDET_FORCE 0 (SAR2_DIG_FORCE)SAR2_DIG_FORCE 0 (SAR2_DATA_INV)SAR2_DATA_INV

Fields

SAR2_CLK_DIV

clock divider
SAR2_SAMPLE_CYCLE

sample cycles for SAR ADC2
SAR2_SAMPLE_BIT

00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for 12-bit width
SAR2_CLK_GATED
SAR2_SAMPLE_NUM
SAR2_PWDET_FORCE
SAR2_DIG_FORCE

1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 controlled by RTC ADC2 CTRL
SAR2_DATA_INV

Invert SAR ADC2 data

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data